The present invention relates to a semiconductor integrated circuit, a method of designing the same, a program recording medium on which a program for supporting designing of the semiconductor integrated circuit is recorded, and a design data recording medium on which design data used for designing the semiconductor integrated circuit is recorded. More particularly, the invention relates to a technique effective for use in a semiconductor integrated circuit suitable for high-speed and low-power operation.
In recent years, a semiconductor integrated circuit device is requested to have improved operating frequency and lower power consumption. In order to improve the operating frequency, generally, the threshold voltage of an insulated gate field effect transistor (hereinbelow, simply called an MIS (Metal Insulated Semiconductor) transistor or a MOS (Metal Oxide Semiconductor) transistor) used in a semiconductor integrated circuit is decreased. When the threshold voltage is set to too low, however, a MOS transistor cannot be completely turned off due to a subthreshold characteristic of the MOS transistor, a subthreshold leak current increases, and a problem such that power consumption of the semiconductor integrated circuit becomes very high occurs. For solving the problem, Japanese Unexamined Patent Publication No. Hei 11(1999)-195976 (first literature) discloses a method of preparing a plurality of kinds of MOS transistors having different threshold voltages and selectively using the MOS transistors in accordance with the degree of timing allowance of a signal path in a semiconductor integrated circuit.
To address the request for reduction in power consumption, Japanese Unexamined Patent Publication No. Hei 10(1998)-189749 (U.S. Pat. No. 6,097,043) (second literature) discloses a method of preparing a plurality of power supply voltages and selectively using a circuit for supplying a high voltage and a circuit for supplying a low voltage, thereby reducing the power.
The method disclosed in the first literature intends to achieve both improvement in operating speed and reduction in leak current in the standby mode by applying a circuit using a MOS transistor of a low threshold voltage to a path having no timing allowance (critical path) and applying a circuit using a MOS transistor having a high threshold voltage to other paths. In a circuit to which the technique is applied, however, when an attempt is made to reduce the power consumption in active operation by decreasing the power supply voltage, the threshold voltage of a MOS transistor has to be also decreased to maintain the operating speed. It was clarified by the examination of the inventors of the present invention that large reduction in power consumption cannot be expected due to the power consumption increased by the leak current in the standby mode.
According to the method disclosed in the second literature, a plurality of power supply voltages are prepared in a semiconductor integrated circuit. By supplying a high voltage to a circuit as a component of a path having no allowance (critical path) and supplying a low voltage to a circuit as a component of a path having an allowance in accordance with the degree of timing allowance of a signal path, the method intends to achieve improved operating speed and reduction in power in active operation. Regarding a circuit to which the technique is applied, however, the inventors of the present invention have uncovered that since a substrate voltage in a MOS transistor to which a high operating voltage is supplied and that in a MOS transistor to which a low operating voltage is supplied are different from each other, an isolating region is necessary in the substrate, and the chip area may increase. Since all of MOS transistors have the same threshold voltage, there is the possibility that power consumption increases due to a leak current in the standby mode.